Microprocessor Architecture for UoP (SE Comp Sem-I 2012 course)

A Guideline for student to understand 80386DX Architecture, Unit II Memory Management Unit and Segment Description, and Paging, 80386DX descriptor tables GDT, Non-pipelined machine cycle, Pipelined machine cycle., Assembly Language Programming, 80386DX instruction set, What is multicore ? Multicore architectures, Intel 64 bit architecture
2nd Revised Edition, by A.P.Godse, D.A.Godse

Book Details

A detail description on 0386DX Architecture History of 8086 microprocessor, Concept of segmentation in 8086, 8086 register block diagram, 80386DX functional block diagram, PIN description, Register set, Flags, Physical address space, Data types. Unit II Memory Management Unit and Segment Description and Paging 80386DX descriptor tables GDT, LDT, IDT, Descriptor cache, Code, Data and stack descriptors, System descriptors, Privilege levels, Segmentation in 80386DX, Comparison of segmentation with 8086, Paging, TSS, Nested tasks, Operating in real mode, Protected mode, Virtual 86 mode, Virtual addressing. Pipelined Architecture Non-pipelined machine cycle, Pipelined machine cycle. Assembly Language Programming 80386DX instruction set, Setting protected mode, Setting v86 mode, Real mode programming New Architectures What is multicore ? Multicore architectures, The software developer's viewpoint, The bus connections, Single core to multicore. Multicore Design Intel 64 bit architecture : Block diagram, Basic execution environment, Data types, Specific advances : Instruction set, Intel microarchitecture code name Nehalem, SIMD instructions, Hyper threading technology, Virtualization technology (Refer TB3) Systems programming, Multiple processor management (Refer RB1)

Additional Information

Edition 2nd Revised Edition
Publisher Technical Publications
ISBN 9789350991046(2)
No. of Pages (Printed Book) 428

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Microprocessor Architecture for UoP (SE Comp Sem-I 2012 course)

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